1. Field of the Invention
This invention relates to a programmable delay line for delaying an input signal for an interval controlled by a digital signal, a programmable delay circuit having the programmable delay line, and to a digital controlled oscillator having the programmable delay circuit.
2. Description of the Prior Art
A delay circuit for delaying an input signal for an interval controlled by a digital signal is known. For, example, Japanese patent publication No. 2-296410 discloses such a delay circuit. This prior art delay circuit comprises a plurality of inverter circuits connected in series and a data selector circuit. A signal to be delayed is inputted to a first stage of the inverter circuits. The data selector circuit supplies either output of the inverters selectively in accordance with a digital signal to supply an output signal.
However, in such a prior art delay circuit, because the delay time is controlled by selecting either output of the series-connected inverter circuits, the ability to increase the range of variation of the delay time is necessarily limited. That is, as the desired range of variation, increases, the number of delay circuits required increases, so that it is difficult to increase a range of variation of the delay time considerably.
A prior art oscillator including such a delay circuit has the same problem.